Den nye Lattice Diamond designsoftware inkluderer bl.a. avanceret support for den nye LatticeECP4 FPGA familie (in english).
Lattice Semiconductor has announced version 2.0 of its Lattice Diamond design software, the flagship design environment for Lattice FPGA products. Version 2.0 includes advanced support for the new LatticeECP4 FPGA family, which redefines the low cost, low power, mid-range FPGA market for cost- and power-sensitive wireless, wireline, video and computing applications.
Lattice Diamond 2.0 design software improves the overall user experience by enabling rapid design timing closure and unveils a new, partition-based incremental design flow for LatticeECP3 FPGA devices. This new design flow will help users preserve design performance and reduce run time after a design change is made.
- Lattice Diamond 2.0 software includes a complete set of easy to use, powerful design tools fine-tuned specifically for the unique logic fabric of our low power, low cost mid-range FPGAs. We’ve added new capabilities like System Planner to support our innovative LatticeECP4 architecture and simplify the creation of complex high-speed 6 Gbps serial data transmission solutions without compromising cost targets, says Mike Kendrick, Lattice’s Director of Software Marketing.
Support for LatticeECP4 FPGA family
The Lattice Diamond design environment enables users to explore design alternatives easily as they target cost-sensitive, low power mid-range FPGA applications – the type ideally suited for the LatticeECP4 family. Lattice Diamond 2.0 software includes advanced data support for timing, power and packaging based on early silicon characterization of the LatticeECP4-190 device.
In addition to algorithms that help ensure low cost and low power implementation, Lattice Diamond version 2.0 adds a new System Planner tool that enables users to optimize the resource usage of the twelve 6Gbps SERDES channels offered on the LatticeECP4 devices.
In addition, the feature-rich power calculator tool provides settings for power save and standby modes, along with pre-emphasis configuration, to accurately analyze and estimate the power consumption of LatticeECP4 designs. Version 2.0 also enables the generation of the LatticeECP4 device’s DSP blocks: the industry’s only FPGA-based high throughput, double data rate DSP blocks, which are ideal for low cost, high performance RF, baseband and image signal processing.
More efficient design flow
Achieving timing closure in the shortest amount of time can be a significant challenge as users put more and more functionality into a single FPGA. When users make a change to their design, they would like the FPGA design tool to preserve some of the critical timing results already achieved and to reduce the overall run time needed to implement the updated design.
Users of LatticeECP3 FPGAs can now use a partition-based incremental design flow to help preserve the performance of their design and reduce the time required for subsequent compile runs needed to implement small design updates. This design flow re-uses previously compiled partitions -- the ones untouched during the re-design -- and re-compiles only the partitions where changes have been introduced.
In addition, in order to achieve fast timing closure, most users are typically required to properly constrain their design. Lattice Diamond 2.0 software now includes an improved, unconstrained paths report that will enable users to more quickly identify and fill gaps in their design constraints.
Improved ease of use
Lattice Diamond software is an intuitive design environment that enables users to complete their design more quickly. To help identify and correct pin usage issues early in the flow, a new pin usage Design Rule Check (DRC) engine was introduced with Lattice Diamond version 1.4. With version 2.0, Lattice Diamond software now detects additional incorrect pin usage cases and supports the LatticeECP4 devices, in addition to the LatticeECP3, MachXO2 and LatticeSC device families. This DRC engine operates either in real-time or on-demand. It also outputs user-friendly reports that help correct pin usage issues by providing users with suggestions.
The Lattice Diamond Programmer and Lattice Diamond Deployment Tool are included in each Lattice Diamond software release. Via an intuitive wizard approach, they enable users to easily program Lattice devices or create the appropriate device programming file in the format required by the user’s deployment method. Starting with Lattice Diamond Programmer 2.0, users can now add their own SPI Flash devices to any new release of the tool.
Lattice Diamond Deployment Tool 2.0 also offers more embedded operations, such as I2C embedded for the MachXO2 device family, and Slave SPI for the LatticeECP3 and LatticeXP2 device families. Both Lattice Diamond Programmer and Lattice Diamond Deployment Tool are also available as standalone tools.
Third party tool support
Lattice Diamond software incorporates Synopsys’ Synplify Pro advanced FPGA synthesis for Windows and Linux. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows.
Support for all Lattice devices is included not only in the OEM versions of Synplify Pro and Active-HDL, but is also available in the full versions of Synopsys Synplify Pro, Aldec Active-HDL and Riviera-PRO. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
Lattice Diamond 2.0 software supports Microsoft Windows XP, Windows Vista and Windows 7 operating systems, and is now also provided as a 64-bit application for Windows 7 to increase memory capacity. For Linux users, Lattice Diamond 2.0 now runs on Linux Red Hat 6 in addition to versions 5 and 4.
Lattice Diamond software can be downloaded from the Lattice website at http://www.latticesemi.com/latticediamond/downloads/ for both Windows and Linux operating systems.